Remote
ASIC DESIGN FOR TEST ENGINEER - Acacia
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The application window is expected to close on 7/14/25. Job posting may be removed earlier if the position is filled or if a sufficient number of applications are received. Meet the TeamAcacia designs intelligent transceivers using advanced signal processing and photonic integration for the 100G, 400G and 1T bit speed fiber optic transmission market deployed in data center, metro, long-haul and ultra-long haul telecommunication networks. This role is within our ASIC team, specifically as part of the Design for Test group. Your ImpactAs a member of Acacia's ASIC team, you will set up and implement MBIST, REPAIR, Boundary Scan, EDT, OCC and SCAN at chip and/or block level and set up pattern generation flow for Scan/ATPG & MBIST/Repair/Fuse.
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