Physical Design Lead Engineer

Application Window Expected to close 04/15/25.

Meet the Team

The Common Hardware Group (CHG) delivers the silicon, optics, and hardware platforms for Cisco's core Switching, Routing, and Wireless products. Come join us and take part in shaping Cisco's ground-breaking solutions by designing, developing and testing some of the most complex ASICs being developed.

Your Impact

As a Technical Leader, you will be responsible for overseeing the design and verification of application-specific integrated circuits (ASICs), ensuring they meet performance, power, and area specifications. This role involves coordinating cross-functional teams, guiding design methodologies, and addressing technical challenges throughout the development process to ensure successful tape-out and compliance with industry standards. Responsibilities include:

• Lead chip-level PNR activities, from floor planning, bump and rdl planning, power grid design to clock planning, routing, and timing closure.
• Perform full chip DRC/LVS/ERC/ANT checks, review and debug the issues, provide solutions and ensure signoff clean results.
• Work closely with block and TOP level physical implementation, IP development teams and to resolve PV issues and address to proper owners.
• Deploy and improve physical verification flows and methodologies. Develop custom check as per need for verification robustness.
• Guide and mentor a team of physical design engineers on project-level backend implementation and partner closely with frontend, integration, and verification teams.

Minimum Qualifications:

• BS/MS in Electrical Engineering or Computer Science, with 10+ year minimum of hands-on experience in ASIC implementation and Physical verification
• Experience in deep submicron CMOS technologies.
• Experience with physical verification (DRC, LVS, ERC, ANT), debug, and solution.
• Scripting experience in TCL, Perl, or Makefile to streamline and automate workflows.
• Experience working with one or more of the following physical design tools, such as Cadence, Innovus, Synopsys IC Compiler, or Fusion Compiler.

Preferred Qualifications:

• Extensive experience working with block or full chip physical verification and/or owning Physical Verification CAD flow development and support.
• Experience on 5nm nodes and below.
• Experience working with semiconductor foundries on installation and maintenance of process design kits (PDKs) for SOC physical design teams.
• Experience working with Package and floorplan teams to define padring and bump-map design.

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