ASIC RTL Design Engineer, Ethernet IP & SoC Integration, AI Hardware

Tesla is accelerating the world's transition to sustainable energy with electric cars, solar and integrated renewable energy solutions for homes and businesses. As part of our AI Hardware team, you will contribute to the development of custom ASICs that power our groundbreaking AI systems, including those for autonomous driving and machine learning training. In this specialized role, you will focus on Ethernet IP integration, SoC clocking and reset architectures, and high-performance data paths within our custom ASICs.This role is located in Palo Alto, CA or Austin, TX.You will work closely with cross-functional teams to deliver innovative hardware solutions that push the boundaries of performance, efficiency, and reliability in AI applications.

Candidate is expected to implement and document microarchitecture specifications tailored to networking and SoC integration, define system-level functional requirements for high-speed data handling, and deliver high-quality RTL designsoptimizedfor AI workloads.

• Design and implement RTL for Ethernet IP integration into custom ASICs, ensuring seamless connectivity and high-throughput data transfer in AI hardware systems
• Develop andoptimizeSoC clocking architectures, including multi-domain clock distribution, synchronization, and power-efficient clock gating techniques
• Architect and implement SoC reset mechanisms, including synchronous/asynchronous resets, reset domain crossing, and fault-tolerant recovery strategies
• Optimizehigh-performance data paths for custom ASICs, focusing on latency reduction, throughput maximization, and integration with DMA engines
• Integrate third-party IPs, such as Ethernet controllers and high-speedserdes, while managing interface protocols like AXI for efficient data movement
• Collaborate with architecture, verification, and physical design teams to define and refine microarchitecture for networking-focused subsystems
• Perform synthesis, timing analysis, and power optimization to meet aggressive performance targets in high-speed protocols
• Debug and resolve issues related to networking concepts, such as packet processing, flow control, and error handling in RTL simulations
• Document designs, specifications, and integration guidelines to support team collaboration and future iterations
• Participate in design reviews, code reviews, and contribute to overall ASIC development flows for AI hardware

• Degree in Electrical Engineering, Computer Engineering, or a related technical field (or equivalent experience)
• 3+ years of experience in ASIC RTL design using Verilog orSystemVerilog
• Strong knowledge of Ethernet protocols (e.g., 10G/25G/100G Ethernet, MAC/PHY layers, and IEEE standards)
• Expertisein high-speed protocols, including PCIe, SerDes, or similar interfaces for data-intensive applications
• Solid understanding of networking concepts, such as switching, routing, QoS, and packet buffering
• Hands-on experience with DMA controllers and high-performance memory access in SoC environments
• Proventrack recordin designing high-performance RTL for compute-intensive or data-heavy systems, with emphasis on pipelining and parallelism
• Proficiencywith AXI/AMBA bus protocols for on-chip interconnects and IP integration
• In-depth knowledge of SoC clocking strategies, including PLLs, clock dividers, and multi-clock domain handling
• Experience with SoC reset architectures, reset sequencing, and safe reset propagation across domains